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0.8 a, low v in , low dropout linear regulator ADP1752/adp1753 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features maximum output current: 0.8 a input voltage range: 1.6 v to 3.6 v low shutdown current: <2 a very low dropout voltage: 70 mv @ 0.8 a load initial accuracy: 1% accuracy over line, load, and temperature: 2% 7 fixed output voltage options with soft start 0.75 v to 2.5 v (ADP1752) adjustable output voltage option with soft start 0.75 v to 3.0 v (adp1753) high psrr 65 db @ 1 khz 65 db @ 10 khz 54 db @ 100 khz 23 v rms at 0.75 v output stable with small 4.7 f ceramic output capacitor excellent load and line transient response current-limit and thermal overload protection power-good indicator logic-controlled enable reverse current protection applications server computers memory components telecommunications equipment network equipment dsp/fpga/microprocessor supplies instrumentation equipment/data acquisition systems typical application circuits top view (not to scale) ADP1752 1 2 3 4 vin vin 100k ? 4.7f 4.7f v in = 1.8 v v out = 1.5 v vin en 12 11 10 9 vout vout vout sense 5 6 7 8 pg gnd ss nc pg 16 15 14 13 vin vin vout vout 10nf 07718-001 figure 1. ADP1752 with fixed output voltage, 1.5 v top view (not to scale) adp1753 1 2 3 4 vin vin 100k ? 4.7f 4.7f v in = 1.8 v v out = 0.5v(1 + r1/r2) vin en 12 11 10 9 vout vout vout adj 5 6 7 8 pg gnd ss nc pg 16 15 14 13 vin vin vout vout 10nf r2 r1 07718-002 figure 2. adp1753 with adjustable output voltage, 0.75 v to 3.0 v general description the ADP1752/adp1753 are low dropout (ldo) cmos linear regulators that operate from 1.6 v to 3.6 v and provide up to 800 ma of output current. these low v in /v out ldos are ideal for regulation of nanometer fpga geometries operating from 2.5 v down to 1.8 v i/o rails, and for powering core voltages down to 0.75 v. using an advanced proprietary architecture, they provide high power supply rejection ratio (psrr) and low noise, and achieve excellent line and load transient response with only a small 4.7 f ceramic output capacitor. the ADP1752 is available in seven fixed output voltage options. the adp1753 is the adjustable version, which allows output voltages that range from 0.75 v to 3.0 v via an external divider. the ADP1752/adp1753 allow an external soft start capacitor to be connected to program the startup. a digital power-good output allows power system monitors to check the health of the output voltage. the ADP1752/adp1753 are available in a 16-lead, 4 mm 4 mm lfcsp, making them not only very compact solutions, but also providing excellent thermal performance for applications that require up to 800 ma of output current in a small, low profile footprint.
ADP1752/adp1753 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical application circuits ............................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? input and output capacitor, recommended specifications .. 4 ? absolute maximum ratings ............................................................ 5 ? thermal data ................................................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configurations and function descriptions ........................... 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 11 ? soft start function (ADP1752/adp1753) ............................. 11 ? adjustable output voltage (adp1753) ................................... 12 ? enable feature ............................................................................ 12 ? power-good feature .................................................................. 12 ? reverse current protection feature ........................................ 13 ? applications information .............................................................. 14 ? capacitor selection .................................................................... 14 ? undervoltage lockout ............................................................... 15 ? current-limit and thermal overload protection ................. 15 ? thermal considerations ............................................................ 15 ? pcb layout considerations ...................................................... 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 19 ? revision history 4/09rev. 0 to rev. a changes to adjustable output voltage accuracy (adp1753) parameter, table 1 ............................................................................. 3 changes to table 3 ............................................................................ 5 10/08revision 0: initial version
ADP1752/adp1753 rev. a | page 3 of 20 specifications v in = (v out + 0.4 v) or 1.6 v (whichever is greater), i out = 10 ma, c in = c out = 4.7 f, t a = 25c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit input voltage range v in t j = ?40c to +125c 1.6 3.6 v operating supply current 1 i gnd i out = 500 a 90 a i out = 100 ma 400 a i out = 100 ma, t j = ?40c to +125c 800 a i out = 0.8 a 0.9 ma i out = 0.8 a, t j = ?40c to +125c 1.2 ma shutdown current i gnd-sd en = gnd, v in = 1.6 v 2 6 a en = gnd, v in = 1.6 v, t j = ?40c to +85c 30 a en = gnd, v in = 3.6 v, t j = ?40c to +85c 100 a output voltage accuracy fixed output voltage accuracy (ADP1752) v out i out = 10 ma ?1 +1 % i out = 10 ma to 0.8 a ?1.5 +1.5 % 10 ma < i out < 0.8 a, t j = ?40c to +125c ?2 +2 % adjustable output voltage accuracy (adp1753) 2 v adj i out = 10 ma 0.495 0.5 0.505 v i out = 10 ma to 0.8 a 0.492 0.508 v 10 ma < i out < 0.8 a, t j = ?40c to +125c 0.490 0.510 v line regulation ?v out /?v in v in = (v out + 0.4 v) to 3.6 v, t j = ?40c to +125c ?0.3 +0.3 %/v load regulation 3 ?v out /?i out i out = 10 ma to 0.8 a, t j = ?40c to +125c 0.8 %/a dropout voltage 4 v dropout i out = 100 ma, v out 1.8 v 10 mv i out = 100 ma, v out 1.8 v, t j = ?40c to +125c 16 mv i out = 0.8 a, v out 1.8 v 70 mv i out = 0.8 a, v out 1.8 v, t j = ?40c to +125c 140 mv start-up time 5 t start-up c ss = 0 nf, i out = 10 ma 200 s c ss = 10 nf, i out = 10 ma 5.2 ms current-limit threshold 6 i limit 1 1.4 5 a thermal shutdown thermal shutdown threshold ts sd t j rising 150 ?c thermal shutdown hysteresis ts sd-hys 15 ?c pg output logic level pg output logic high pg high 1.6 v v in 3.6 v, i oh < 1 a 1.0 v pg output logic low pg low 1.6 v v in 3.6 v, i ol < 2 ma 0.4 v pg output delay from en transition low to high 1.6 v v in 3.6 v, c ss = 10 nf 5.5 ms pg output threshold output voltage falling pg fall 1.6 v v in 3.6 v ?10 % output voltage rising pg rise 1.6 v v in 3.6 v ?6.5 % en input en input logic high v ih 1.6 v v in 3.6 v 1.2 v en input logic low v il 1.6 v v in 3.6 v 0.4 v en input leakage current v i-leakage en = vin or gnd 0.1 1 a undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 1.58 v input voltage falling uvlo fall t j = ?40c to +125c 1.25 v hysteresis uvlo hys t j = 25c 100 mv soft start current i ss 1.6 v v in 3.6 v 0.6 0.9 1.2 a adj input bias current (adp1753) adj i-bias 1.6 v v in 3.6 v, t j = ?40c to +125c 10 150 na sense input bias current sns i-bias 1.6 v v in 3.6 v 10 a
ADP1752/adp1753 rev. a | page 4 of 20 parameter symbol test conditions/comments min typ max unit output noise out noise 10 hz to 100 khz, v out = 0.75 v 23 v rms 10 hz to 100 khz, v out = 2.5 v 65 v rms power supply rejection ratio psrr v in = v out + 1 v, i out = 10 ma 1 khz, v out = 0.75 v 65 db 1 khz, v out = 2.5 v 56 db 10 khz, v out = 0.75 v 65 db 10 khz, v out = 2.5 v 56 db 100 khz, v out = 0.75 v 54 db 100 khz, v out = 2.5 v 51 db 1 minimum output load current is 500 a. 2 accuracy when vout is connected directly to adj. when vout voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. 3 based on an end-point calculation using 10 ma and 0.8 a loads. see fi gure 6 for typical load regulation performance. 4 dropout voltage is defined as the input to output voltage differ ential when the input voltage is set to the nominal output vol tage. this applies only to output voltages above 1.6 v. 5 start-up time is defined as the time between the rising edge of en to v out being at 95% of its nominal value. 6 current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 1.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 1.0 v, or 0.9 v. input and output capacitor, recommended specifications table 2. parameter symbol test conditions/comments min typ max unit minimum input and output capacitance 1 c min t a = ?40c to +125c 3.3 f capacitor esr r esr t a = ?40c to +125c 0.001 0.1 1 the minimum input and output capacitance should be greater than 3. 3 f over the full range of operating conditions. the full r ange of operating conditions in the application must be considered during devi ce selection to ensure that the minimum capa citance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with this ldo.
ADP1752/adp1753 rev. a | page 5 of 20 absolute maximum ratings table 3. parameter rating vin to gnd ?0.3 v to +3.6 v vout to gnd ?0.3 v to +3.6 v en to gnd ?0.3 v to +3.6 v ss to gnd ?0.3 v to +3.6 v pg to gnd ?0.3 v to +3.6 v sense/adj to gnd ?0.3 v to +3.6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the ADP1752/adp1753 may be damaged if the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient tempera- ture may need to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). t j is calculated using the following formula: t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in 3 in circuit board. refer to jedec jesd51-7 for detailed information about board construction. for more information, see the an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) at www.analog.com . jb is the junction-to-board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12 document, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than through a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and the power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) refer to the jedec jesd51-8 and jesd51-12 documents for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 16-lead lfcsp with exposed pad (cp-16-4) 130 32.7 c/w esd caution
ADP1752/adp1753 rev. a | page 6 of 20 pin configurations and function descriptions pin 1 indicator 1 vin 2 vin 3 vin 4 en 11 vout 12 vout 10 vout 9sense 5 pg 6 gnd 7 ss 8 n c 15 vin 16 vin 14 vou t 13 vou t top view (not to scale) ADP1752 notes 1. nc = no connect. 2 . the exposed pad on the bottom of the lfcsp enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connected to the ground plane on the board. 07718-003 pin 1 indicator 1 vin 2 vin 3 vin 4 en 11 vout 12 vout 10 vout 9adj 5 pg 6 gnd 7 ss 8 n c 15 vin 16 vin 14 vou t 13 vou t top view (not to scale) adp1753 notes 1. nc = no connect. 2 . the exposed pad on the bottom of the lfcsp enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connected to the ground plane on the board. 07718-004 figure 3. ADP1752 pin configuration figure 4. adp1753 pin configuration table 5. pin function descriptions ADP1752 pin no. adp1753 pin no. mnemonic description 1, 2, 3, 15, 16 1, 2, 3, 15, 16 vin regulator input supply. bypass vin to gnd with a 4.7 f or greater capacitor. note that all five vin pins must be connected to the source. 4 4 en enable input. drive en high to turn on the regula tor; drive it low to turn off the regulator. for automatic startup, connect en to vin. 5 5 pg power good. this open-drain output requires an exte rnal pull-up resistor to vin. if the part is in shutdown mode, current-limit mode, therma l shutdown, or if it falls below 90% of the nominal output voltage, pg immediately transitions low. 6 6 gnd ground. 7 7 ss soft start. a capacitor connected to this pin determines the soft start time. 8 8 nc not connected. no internal connection. 9 n/a sense sense. this pin measures the actual output volt age at the load and feeds it to the error amplifier. connect sense as close as possible to the load to minimize the effect of ir drop between the regulator output and the load. n/a 9 adj adjust. a resistor divider from vout to adj sets the output voltage. 10, 11, 12, 13, 14 10, 11, 12, 13, 14 vout regulated output voltage. bypass vout to gnd with a 4.7 f or greater capacitor. note that all five vout pins must be connected to the load. 17 (epad) 17 (epad) exposed paddle (epad) the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connected to the ground plane on the board.
ADP1752/adp1753 rev. a | page 7 of 20 typical performance characteristics v in = 1.9 v, v out = 1.5 v, i out = 10 ma, c in = 4.7 f, c out = 4.7 f, t a = 25c, unless otherwise noted. 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 ?40 ?5 25 85 125 output voltage (v) junction temperature (c) load = 10ma load = 100ma load = 400ma load = 800ma 07718-105 figure 5. output voltage vs. junction temperature 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 10 100 1k output voltage (v) load current (ma) 07718-106 figure 6. output volt age vs. load current 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 1.8 3.63.43.23.02.8 2.6 2.42.22.0 output voltage (v) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma 07718-107 figure 7. output voltage vs. input voltage 1000 900 800 700 600 500 400 300 200 100 0 ?40 ?5 25 85 125 ground current (a) junction temperature (c) load = 10ma load = 100ma load = 400ma load = 800ma 07718-108 figure 8. ground current vs. junction temperature 1000 900 800 700 600 500 400 300 200 100 0 10 100 1k ground current (a) load current (ma) 07718-109 figure 9. ground current vs. load current 1000 900 800 700 600 500 400 300 200 100 0 1.8 3.63.43.23.02.8 2.6 2.42.22.0 ground current (a) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma 07718-110 figure 10. ground current vs. input voltage
ADP1752/adp1753 rev. a | page 8 of 20 100 90 70 80 60 50 40 30 20 10 0 ?40 85 60 35 10 ?15 shutdown current (a) temperature (c) 1.9v 2.0v 2.4v 2.6v 3.0v 3.6v 07718-111 figure 11. shutdown current vs. temperature at various input voltages 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1 10 100 1k load current (ma) dropout voltage (v) 1.6v 2.5v 07718-112 figure 12. dropout voltage vs. load current, v out = 1.6 v, 2.5 v 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.3 2.4 2.5 2.6 2.7 2.8 output voltage (v) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma 07718-113 figure 13. output voltage vs. input voltage (in dropout), v out = 2.5 v 4500 4000 3500 3000 2500 2000 1500 1000 500 0 2.3 2.4 2.5 2.6 2.7 2.8 ground current (a) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma 07718-114 figure 14. ground current vs. input voltage (in dropout), v out = 2.5 v ch1 500ma ? b w ch2 50mv b w m10s a ch1 380ma 1 2 t 10.20% t i load 1ma to 800ma load step, 2.5a/s, 500ma/div v out 50mv/div v in = 3.6v v out = 1.5v 07718-115 figure 15. load transient response, c in = 4.7 f, c out = 4.7 f ch1 500ma ? b w ch2 20mv b w m10s a ch1 530ma 1 2 t 10.20% t i load 1ma to 800ma load step, 2.5a/s, 500ma/div v out 20mv/div v in = 3.6v v out = 1.5v 07718-116 figure 16. load transient response, c in = 22 f, c out = 22 f
ADP1752/adp1753 rev. a | page 9 of 20 ch1 500mv b w ch2 2.0mv b w m10s a ch4 800ma 1 2 t 9.40% t v in 3v to 3.5v input voltage step, 2v/s v out 2mv/div v out = 1.5v c in = c out = 4.7f 07718-117 figure 17. line transient resp onse, load current = 800 ma 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 noise (v rms) load current (a) 0.75v 1.5v 2.5v 07718-118 figure 18. noise vs. load current and output voltage 10 1 0.1 0.01 10 100 1k 10k 100k noise spectral density (v/ hz) frequency (hz) 0.75v 1.5v 2.5v 07718-119 figure 19. noise spectral density vs. output voltage, i load = 10 ma 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 800ma 400ma 100ma 10ma 07718-120 figure 20. power supply reject ion ratio vs. frequency, v out = 0.75 v, v in = 1.75 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) load = 800ma load = 400ma load = 100ma load = 10ma 07718-121 figure 21. power supply rejection ratio vs. frequency, v out = 1.5 v, v in = 2.5 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) load = 800ma load = 400ma load = 100ma load = 10ma 07718-122 figure 22. power supply reject ion ratio vs. frequency, v out = 2.5 v, v in = 3.5 v
ADP1752/adp1753 rev. a | page 10 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 1.5v/800ma 2.5v/800ma 0.75v/800ma 1.5v/10ma 2.5v/10ma 0.75v/10ma 07718-123 figure 23. power supply rejection ratio vs. frequency and output voltage
ADP1752/adp1753 rev. a | page 11 of 20 theory of operation the ADP1752/adp1753 are low dropout linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (psrr) and excellent line and load transient response with only a small 4.7 f ceramic output capacitor. both devices operate from a 1.6 v to 3.6 v input rail and provide up to 0.8 a of output current. supply current in shutdown mode is typically 2 a. uvlo vout vin sense ss short-circuit and thermal protection r1 0.5v ref r2 shutdown en pg gnd ADP1752 reverse polarity protection pg detect 0.9a 0 7718-019 figure 24. ADP1752 internal block diagram uvlo vout vin adj ss short-circuit and thermal protection 0.5v ref shutdown en pg gnd adp1753 reverse polarity protection pg detect 0.9a 0 7718-020 figure 25. adp1753 internal block diagram internally, the ADP1752/adp1753 consist of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass transistor, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the ADP1752 is available in seven fixed output voltage options between 0.75 v and 2.5 v. the ADP1752 allows for connection of an external soft start capacitor that controls the output voltage ramp during startup. the adp1753 is the adjustable version with an output voltage that can be set to a value between 0.75 v and 3.0 v by an external voltage divider. both devices are con- trolled by an enable pin (en). soft start functi on (ADP1752/adp1753) for applications that require a controlled startup, the ADP1752/ adp1753 provide a programmable soft start function. the programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. to implement soft start, connect a small ceramic capacitor from ss to gnd. upon startup, a 0.9 a current source charges this capacitor. the ADP1752/adp1753 start-up output voltage is limited by the voltage at ss, providing a smooth ramp-up to the nominal output voltage. the soft start time is calculated as follows: t ss = v ref ( c ss / i ss ) (1) where: t ss is the soft start period. v ref is the 0.5 v reference voltage. c ss is the soft start capacitance from ss to gnd. i ss is the current sourced from ss (0.9 a). when the ADP1752/adp1753 are disabled (using en), the soft start capacitor is discharged to gnd through an internal 100 resistor. 2.50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 0246810 voltage (v) time (ms) en 1nf 4.7nf 10nf 07718-021 figure 26. v out ramp-up with external soft start capacitor
ADP1752/adp1753 rev. a | page 12 of 20 ch1 2.0v b w ch2 500mv b w m40s a ch1 920mv 1 2 t 9.8% t en v out 500mv/div v out = 1.5v c in = c out = 4.7f 07718-022 figure 27. v out ramp-up with internal soft start adjustable output voltage (adp1753) the output voltage of the adp1753 can be set over a 0.75 v to 3.0 v range. the output voltage is set by connecting a resistive voltage divider from vout to adj. the output voltage is calcu- lated using the following equation: v out = 0.5 v (1 + r1 / r2 ) (2) where: r1 is the resistor from vout to adj. r2 is the resistor from adj to gnd. the maximum bias current into adj is 150 na. therefore, to achieve less than 0.5% error due to the bias current, use values less than 60 k for r2. enable feature the ADP1752/adp1753 use the en pin to enable and disable the vout pin under normal operating conditions. as shown in figure 28, when a rising voltage on en crosses the active threshold, vout turns on. when a falling voltage on en crosses the inactive threshold, vout turns off. 2 ch1 500mv b w ch2 500mv b w m2.0ms a ch1 1.05v 1 t 29.6% t en v out 500mv/div v out = 1.5v c in = c out = 4.7f 07718-023 figure 28. typical en pin operation as shown in figure 28, the en pin has hysteresis built in. this hysteresis prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the vin voltage. therefore, these thresholds vary with changing input voltage. figure 29 shows typical en active/inactive thresholds when the input voltage varies from 1.6 v to 3.6 v. 1.1 0.5 0.6 0.7 0.8 0.9 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 en threshold (v) input voltage (v) en active en inactive 07718-024 figure 29. typical en pin thresholds vs. input voltage power-good feature the ADP1752/adp1753 provide a power-good pin, pg, to indicate the status of the output. this open-drain output requires an external pull-up resistor to v in . if the part is in shutdown, in current limit mode, in thermal shutdown, or if it falls below 90% of the nominal output voltage, pg immediately transitions low. during soft start, the rising threshold of the power-good signal is 93.5% of the nominal output voltage. the open-drain output is held low when the ADP1752/adp1753 have sufficient input voltage to turn on the internal pg transistor. an optional soft start delay can be detected. the pg transistor is terminated via a pull-up resistor to v out or v in . power-good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. regulator input voltage brownouts or glitches trigger a power no-good if v out falls below 90%. a normal power-down triggers a power no-good when v out drops below 90%.
ADP1752/adp1753 rev. a | page 13 of 20 2 2 ch1 1.0v b w ch3 1.0v b w ch2 500mv b w m40.0s a ch3 900mv 1 t 50.40% t v in 1v/div v out 500mv/div pg 1v/div v out = 1.5v c in = c out = 4.7f 07718-025 figure 30. typical pg behavior vs. v out , v in rising (v out = 1.5 v) 2 2 ch1 1.0v b w ch3 1.0v b w ch2 500mv b w m40.0s a ch3 900mv 1 t 50.40% t v in 1v/div v out 500mv/div pg 1v/div v out = 1.5v c in = c out = 4.7f 07718-026 figure 31. typical pg behavior vs. v out , v in falling (v out = 1.5 v) reverse current protection feature the ADP1752/adp1753 have additional circuitry to protect against reverse current flow from vout to vin. for a typical ldo with a pmos pass device, there is an intrinsic body diode between vin and vout. when v in is greater than v out , this diode is reverse-biased. if v out is greater than v in , the intrinsic diode becomes forward-biased and conducts current from vout to vin, potentially causing destructive power dissipation. the reverse current protection circuitry detects when v out is greater than v in and reverses the direction of the intrinsic diode connec- tion, reverse-biasing the diode. the gate of the pmos pass device is also connected to vout, keeping the device off. figure 32 shows a plot of the reverse current vs. the v out to v in differential. 4000 3500 3000 2500 2000 1500 1000 500 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 reverse current (a) v out ? v in (v) 07718-232 figure 32. reverse current vs. v out ? v in
ADP1752/adp1753 rev. a | page 14 of 20 applications information capacitor selection output capacitor the ADP1752/adp1753 are designed for operation with small, space-saving ceramic capacitors, but they can function with most commonly used capacitors as long as care is taken with the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a mini- mum of 3.3 f capacitance with an esr of 500 m or less is recommended to ensure the stability of the ADP1752/adp1753. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ADP1752/adp1753 to large changes in load current. figure 33 and figure 34 show the transient responses for output capacitance values of 4.7 f and 22 f, respectively. ch1 500ma ? b w ch2 50mv b w m1s a ch1 380ma 1 2 t 11.6% t i load 1ma to 800ma load step, 2v/s, 500ma/div v out 50mv/div v in = 3.6v, v out = 1.5v c in = c out = 4.7f 07718-132 figure 33. output transient response, c out = 4.7 f ch1 500ma ? b w ch2 20mv b w m1s a ch1 530ma 1 2 t 12.2% t i load 1ma to 800ma load step, 2v/s, 500ma/div v out 20mv/div v in = 3.6v, v out = 1.5v c in = c out = 22f 07718-133 figure 34. output transient response, c out = 22 f input bypass capacitor connecting a 4.7 f capacitor from the vin pin to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if output capacitance greater than 4.7 f is required, it is recommended that the input capacitor be increased to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the ADP1752/adp1753, as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor tempera- ture and dc bias characteristics. figure 35 shows the capacitance vs. voltage bias characteristics of an 0805 case, 4.7 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c temperature range and is not a function of package size or voltage rating. 5 4 3 2 1 0 0246810 capacitance (f) voltage bias (v) murata p/n grm219r61a475ke34 07718-029 figure 35. capacitance vs. voltage bias characteristics equation 3 can be used to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol) (3) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance.
ADP1752/adp1753 rev. a | page 15 of 20 in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out = 4.46 f at 1.8 v, as shown in figure 35. substituting these values in equation 3 yields c eff = 4.46 f (1 ? 0.15) (1 ? 0.1) = 3.41 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temper- ature and tolerance at the chosen output voltage. to guarantee the performance of the ADP1752/adp1753, it is imperative that the effects of dc bias, temperature, and toler- ances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the ADP1752/adp1753 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 1.58 v. this ensures that the adp1753/adp1753 inputs and the output behave in a predicta- ble manner during power-up. current-limit and thermal overload protection the ADP1752/adp1753 are protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. the ADP1752/adp1753 are designed to reach current limit when the output load reaches 1.4 a (typical). when the output load exceeds 1.4 a, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c (typical), the output is turned on again and the output current is restored to its nominal value. consider the case where a hard short from vout to ground occurs. at first, the ADP1752/adp1753 reach current limit so that only 1.4 a is conducted into the short. if self-heating of the junction becomes great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 1.4 a into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 1.4 a and 0 a that continues as long as the short remains at the output. current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation should be externally limited so that junction temperatures do not exceed 125c. thermal considerations to guarantee reliable operation, the junction temperature of the ADP1752/adp1753 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient tempera- ture, power dissipation in the power device, and thermal resistance between the junction and ambient air ( ja ). the ja value is depen- dent on the package assembly compounds used and the amount of copper to which the gnd pin and the exposed pad (epad) of the package are soldered on the pcb. table 6 shows typical ja values for the 16-lead lfcsp for various pcb copper sizes. table 7 shows typical jb values for the 16-lead lfcsp. table 6. typical ja values copper size (mm 2 ) ja (c/w), lfcsp 0 1 130 100 80 500 69 1000 54 6400 42 1 device soldered to minimum size pin traces. table 7. typical jb values copper size (mm 2 ) jb (c/w) @ 1 w 100 32.7 500 31.5 1000 25.5 the junction temperature of the ADP1752/adp1753 can be calculated from the following equation: t j = t a + ( p d ja ) (4) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [(v in ? v out ) i load ] + ( v in i gnd ) (5) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation can be simplified as follows: t j = t a + {[( v in ? v out ) i load ] ja } (6) as shown in equation 6, for a given ambient temperature, input- to-output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperature does not rise above 125c. figure 36 thro ugh figure 41 show junction temperature calculations for different ambient temperatures, load currents, v in to v out differ entials, and areas of pcb copper.
ADP1752/adp1753 rev. a | page 16 of 20 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-135 figure 36. 6400 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-136 figure 37. 500 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-137 figure 38. 0 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-138 figure 39. 6400 mm 2 of pcb copper, t a = 50c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-139 figure 40. 500 mm 2 of pcb copper, t a = 50c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-140 figure 41. 0 mm 2 of pcb copper, t a = 50c, lfcsp
ADP1752/adp1753 rev. a | page 17 of 20 in cases where the board temperature is known, the thermal characterization parameter, jb , can be used to estimate the junction temperature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (7) figure 42 through figure 45 show junction temperature calcula- tions for different board temperatures, load currents, v in to v out differentials, and areas of pcb copper. 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 100ma load = 50ma load = 10ma load = 400ma load = 200ma 07718-141 figure 42. 500 mm 2 of pcb copper, t b = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 400ma load = 200ma load = 100ma load = 50ma load = 10ma 07718-142 figure 43. 500 mm 2 of pcb copper, t b = 50c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 400ma load = 200ma load = 100ma load = 50ma load = 10ma 07718-143 figure 44. 1000 mm 2 of pcb copper, t b = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 800ma load = 400ma load = 200ma load = 100ma load = 50ma load = 10ma 07718-144 figure 45. 1000 mm 2 of pcb copper, t b = 50c, lfcsp
ADP1752/adp1753 rev. a | page 18 of 20 pcb layout considerations heat dissipation from the package can be improved by increas- ing the amount of copper attached to the pins of the ADP1752/ adp1753. however, as shown in table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. here are a few general tips when designing pcbs: ? place the input capacitor as close as possible to the vin and gnd pins. ? place the output capacitor as close as possible to the vout and gnd pins. ? place the soft start capacitor as close as possible to the ss pin. ? connect the load as close as possible to the vout and sense pins (adp1754) or to the vout and adj pins (adp1755). use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 0 7718-233 figure 46. evaluation board 07718-145 figure 47. typical bo ard layouttop side 0 7718-146 figure 48. typical board layoutbottom side
ADP1752/adp1753 rev. a | page 19 of 20 outline dimensions compliant to jedec standards mo-220-vggc 2 . 2 5 2 . 1 0 s q 1 . 9 5 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 (bottom view) 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.25 min 072808-a 0.75 0.60 0.50 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 49. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters ordering guide model temperature range output voltage (v) package description package option ADP1752acpz-0.75r7 1 ?40c to +125c 0.75 16-lead lfcsp_vq cp-16-4 ADP1752acpz-1.0-r7 1 ?40c to +125c 1.0 16-lead lfcsp_vq cp-16-4 ADP1752acpz-1.1-r7 1 ?40c to +125c 1.1 16-lead lfcsp_vq cp-16-4 ADP1752acpz-1.2-r7 1 ?40c to +125c 1.2 16-lead lfcsp_vq cp-16-4 ADP1752acpz-1.5-r7 1 ?40c to +125c 1.5 16-lead lfcsp_vq cp-16-4 ADP1752acpz-1.8-r7 1 ?40c to +125c 1.8 16-lead lfcsp_vq cp-16-4 ADP1752acpz-2.5-r7 1 ?40c to +125c 2.5 16-lead lfcsp_vq cp-16-4 adp1753acpz-r7 1 ?40c to +125c adjustable from 0.75 to 3.0 16-lead lfcsp_vq cp-16-4 ADP1752-1.5-evalz 1 1.5 evaluation board adp1753-evalz 1 adjustable evaluation board 1 z = rohs compliant part.
ADP1752/adp1753 rev. a | page 20 of 20 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07718-0-4/09(a)

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